Generate For vs. For

generate for

generate for 1

 1
 2
 3
 4
 5
 6
 7
 8
 9
10
11
12
13
14
15
16
17
18


module generate_for1(
input logic clk,
input  logic in,
output logic [3:0]out
    );

genvar i;   

generate 
for(i=1;i<=3;i=i+1) begin
always_ff@(posedge clk) begin
out[0]<=in;

out[i]<=out[i-1];
end
end
endgenerate
endmodule

generate1

generate for2

 1
 2
 3
 4
 5
 6
 7
 8
 9
10
11
12
13
14
15
16
17
18


module generate_for1(
input logic clk,
input  logic in,
output logic [3:0]out
    );

genvar i;   

generate 
for(i=0;i<=3;i=i+1) begin
always_ff@(posedge clk) begin
//out[0]<=in;

out[i]<=out[i-1];
end
end
endgenerate
endmodule

generate2

草率了，忘记数组不能负索引了，但是负索引竟然可以综合

generate for3

 1
 2
 3
 4
 5
 6
 7
 8
 9
10
11
12
13
14
15
16
17
18
19
20
21
22


module generate_for1(
input logic clk,
input  logic in,
output logic [3:0]out
    );

genvar i;   

generate 
for(i=1;i<=3;i=i+1) begin
always_ff@(posedge clk) begin
//out[0]<=in;
out[i]<=out[i-1];
end
always_ff@(posedge clk) begin
out[0]<=in;
end


end
endgenerate
endmodule

generate3

generate for 4

 1
 2
 3
 4
 5
 6
 7
 8
 9
10
11
12
13
14
15
16
17
18
19
20


module generate_for1(
input logic clk,
input  logic in,
output logic [3:0]out
    );

genvar i;   

generate 
for(i=1;i<=3;i=i+1) begin
always_ff@(posedge clk) begin
//out[0]<=in;
out[i]<=out[i-1];
end
end
endgenerate
always_ff@(posedge clk) begin
out[0]<=in;
end
endmodule

generate4

for

for1

 1
 2
 3
 4
 5
 6
 7
 8
 9
10
11
12
13
14
15


module for1(
input logic clk,
input  logic in,
output logic [3:0]out
    );

integer i;   
always_ff@(posedge clk) begin
out[0]<=in;
for(i=1;i<=3;i=i+1) begin 
out[i]<=out[i-1];
end

end 
endmodule

for1

for2

 1
 2
 3
 4
 5
 6
 7
 8
 9
10
11
12
13
14
15


module for1(
input logic clk,
input  logic in,
output logic [3:0]out
    );

integer i;   
always_ff@(posedge clk) begin
out[0]<=in;
for(i=0;i<=3;i=i+1) begin 
out[i]<=out[i-1];
end

end 
endmodule

for2

草率了，忘记数组不能负索引了，但是负索引竟然可以综合